Hi all,
I'm trying to access a verilog hierarchy which was generated by a generate block - but I'm having some problems with it. for example:
verilog file: (let's assume it is located at "testbench" hierarchy, and an interface named "some_interface" is already defined)
genvar i;
generate
for (i=0;i<3;i++)
begin : GENERATE_HEADER
some_interface some_interface_inst(clk);
assign some_interface_inst.x=1'b0;
assign some_interface_inst.y=1'b1;
end
endgenerate
systemverilog file:
virtual some_interface some_interface_arr[0:2];
for (int i=0;i<3;i++)
some_interface_arr[i]=testbench.GENERATE_HEADER[i].some_interface_inst;
I believe I can't access a generated verilog hierarchy with a system-verilog for loop (variable i). Am I correct? and if so - is there a way to pass this obstacle?
Thanks in advance,
Eyal.
P.s - What I'm generally trying to do is to get handles to the instantiated interfaces (some_interface) and pass them to system verilog objects in my testbench, using the virtual interface array.