Assertion experts,
I know how to do a check of new_data_io (see below) in terms of 'regular' SV code, but will someone comment on how/if I can put this into a nice assertion to put into my interface?
All based on posedge clk:
valid_io - indicates valid data data_io - the data new_data_io - signifies that data_io has changed since the previous valid_io cycle
So, when (valid_io && (!new_data_io)), the receiver can just use the most recently valid data.
(The fact that there can be cycles of !valid_io, while this assertion is active, is what's throwing me off. Well, and also the concept of retaining previous state of data_io. Perhaps this might not be suitable for an assertion and I should just stick with a small process to do the check.)
thx for any feedback,
Assertion Novice
(Why ever did I loan out my book Art of Verification with SystemVerilog Assertions by Faisal Haque?)