UVM SystemVerilog Register Layer Basics Video Series

One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer.

The new video series is broken up into twelve clips:

1. Introduction
2. Testbench Integration
3. Adapter
4. Predictor & Auto Predict
5. Register Model & Generation
6. IP-XACT
7. Register Model Classes
8. Register API & Sequences
9. Access Policies
10. Frontdoor & Backdoor
11. Predefined Sequences
12. Demonstration

You are now registered for success!  (sorry, bad pun.  )

=Adam Sherilog, Cadence