What is the best way to measure simulation time using VCS?
I would like to do some same-tool benchmarks to measure simulation performance improvements using different coding styles or tricks using the same simulator.
I do not intend to do cross-tool benchmarking; only same-tool benchmarking. I will check to see if techniques used with one tool also cause similar performance improvements across multiple tools, but I will not report actual speed differences between the tools (in accordance with my tool-usage agreements with multiple vendors).
I am trying to identify best performance coding practices.
The best technique I currently have is to do: "time simv"
This reports: real / user / sys times.
Regards - Cliff Cummings
Verilog & SystemVerilog Guru