Compilation error in IUS9.2-S023

Hello,

    I am trying to simulate i2c top file which contains a sequence in which i have raised objection and dropped objection in the body of the sequence as follows: I am facing compilation issues such as "starting_phase" is undeclared identifier whereas the code compiles fine with questasim. Is IUS version 9.2_s023 compatible with uvm-1.1a? Is there any additional switch required to run ?

Command given : irun -uvm i2c_top.sv

Code Snippet

---------------------

i2c_top.sv

========

`include "uvm_pkg.sv"

 import uvm_pkg::* ;

 `include "uvm_macros.svh"

 `include i2c_txn.sv

 `include i2c_interface.sv

  `include i2c_sequence.sv

i2c_sequence.sv

=============

task body()

if(starting_phase!=null)

  starting_phase.raise_objection(this);

    repeat(1)

      begin

        req=i2c_txn::type_id::create(req);

       start_item(req)

       finish_item(req)

     end

if(starting_phase!=null)

   starting_phase.drop_objection(this)

Error snippet

--------------------

i2c_top.sv
      if(starting_phase!=null)
                      |
ncvlog: *E,UNDIDN (i2c_slave_sequence.sv,10|22): 'starting_phase': undeclared identifier [12.5(IEEE)].
      if(starting_phase!=null)
                      |

ncvlog: *E,UNDIDN (i2c_slave_sequence.sv,54|22): 'starting_phase': undeclared identifier [12.5(IEEE)].
  uvm_config_db#(virtual i2c_if)::set(uvm_root::get(), "*", "i2c_vif", intf);
              |
ncvlog: *E,NOPBIND (i2c_top.sv,40|14): Package uvm_config_db could not be bound.
        module worklib.i2c_top:sv
                errors: 1, warnings: 0
        Total errors/warnings found outside modules and primitives:
                errors: 4, warnings: 0