Accessing SystemC from SystemVerilog TB

Hi All,

I have a basic SystemC TB which has VHDL DUT and some systemC TB components instantiated.

Now I want to build a SystemVerilog UVM TB on top of this systemC TB.

1. Is it possible to do this?

2. How to access systemC TB components (like systemC threads, systemC variables & systemC events, etc..) from SystemVerilog TB?

Please help to clarify this basic query.

Thanks in advance!