In uvm_reg_map::do_bus_read() task, after the call to adapter.bus2reg() function, do_bus_read() function checks for any Xs in data field.
Code from uvm_reg_map:
uvm_reg_bus_op rw_access;
uvm_reg_data_logic_t data;
data = rw_access.data & ((1<<bus_width*8)-1);
rw.status = rw_access.status;
if (rw.status == UVM_IS_OK && (^data) === 1'bx)
rw.status = UVM_HAS_X;
Here, rw_access.data is of type "bit" and is assigned to data which is of type "logic". and then data is checked for Xs. But, as rw_access.data is "bit" type, it will never contain Xs or Zs.
As a result, data will never have Xs, so rw.status will not set to UVM_HAS_X. So even if bus2reg function samples Xs from the bus, those Xs never make upto tasks in uvm_reg_map class.
Some supporting code::
uvm_reg_defines.svh: `define UVM_REG_DATA_TYPE bit
uvm_reg_model.svh : typedef `UVM_REG_DATA_TYPE unsigned [`UVM_REG_DATA_WIDTH-1:0] uvm_reg_data_t ;
uvm_reg_item.svh:
typedef struct {
uvm_access_e kind;
uvm_reg_addr_t addr;
uvm_reg_data_t data;
int n_bits;
uvm_reg_byte_en_t byte_en;
uvm_status_e status;
} uvm_reg_bus_op;
In my testbench, I want uvm_reg_map to set the status to UVM_HAS_X whenever data received for a register read transaction from DUT is X. How do I achieve that?