Hi,
When using ralfgen to generate uvm register models, the whole model is generated in one big file, include all the submodules.
This affect the reusability. I would prefer to reuse model that were generated for submodules instead.
As an example, here is a basic hierachical structure of a system:
Module A
|-Module x
with their corresponding ralf file:
ModuleA_regmodel.ralf:
source Modulex.ralf
system ModuleA_regmodel {
bytes 4
block Modulex = my_modulex@0X000000
}
Modulex_regmodel.ralf:
block Modulex_regmodel{
bytes 4
register dummy {
bytes 4;
}
}
Running ralfgen will give me the following uvm regmodel in moduleA_regmodel.sv
`ifndef RAL_MODULEA_REGMODEL `define RAL_MODULEA_REGMODEL import uvm_pkg::*; class ral_reg_modulex_regmodel_dummy extends uvm_reg; [...] endclass : ral_reg_modulex_regmodel_dummy class ral_block_modulex_regmodel extends uvm_reg_block; [...] endclass : ral_block_modulex_regmodel class ral_sys_modulea_regmodel extends uvm_reg_block; [...] endclass : ral_sys_modulea_regmodel `endif
Now, for reusability, it would be preferrable to have two files instead:
modulex_regmodel.sv
`ifndef RAL_MODULEA_REGMODEL `define RAL_MODULEA_REGMODEL import uvm_pkg::*; class ral_reg_modulex_regmodel_dummy extends uvm_reg; [...] endclass : ral_reg_modulex_regmodel_dummy class ral_block_modulex_regmodel extends uvm_reg_block; [...] endclass : ral_block_modulex_regmodel `endif
moduleA_regmodel.sv
`ifndef RAL_MODULEA_REGMODEL `define RAL_MODULEA_REGMODEL import uvm_pkg::*; class ral_sys_modulea_regmodel extends uvm_reg_block; rand ral_block_modulex_regmodel my_modulex; [...] endclass : ral_sys_modulea_regmodel `endif
Now, is there a way to generate moduleA_regmodel as is, without deleting the modulex_regmodel class declaration after each generation?
I was thinking of having a modulex_regmodel_empty.ralf:
block Modulex_regmodel{
}
And source it in ModuleA_regmodel.ralf, but I get an error.
Other ideas?
Thank you!