FSM testbench

Hi all, i'm new both to this forum and to the verification (and electronic in general) world.

My problem is that i'm not carrying out a good tb for my design. More specifically my DUT is a FSM in which the concept of transaction is not well defined (i have a lot of signals through different interfaces and, basically, they must match clock by clock the desired values). In order to test the dut's outputs my idea was to replicate (without knowing the design code) the fsm in the scoreboard and so test dut's output againts scoreaboad's output. The problem arises here: when  and how i have to update my fsm? My previous approach was to have a set of monitors for the dut's input and a set of monitors for dut's output and, basically, the code of my scoreboard had this structure 

forever begin
   fifo_input_1.get(tr_input_1);
   fifo_input_2.get(tr_input_2);

   update_fsm(tr_input_1, tr_input_2);

   fifo_output_1.get(tr_output_1);
   fifo_output_2.get(tr_output_2);

   check_output(tr_output_1, tr_output2);
end

in which the fsm was updated every clock because each monitor produce a transaction at each clock.

Of cource this is a very bad approach, i suppose....

What is the best architecture choice to do what i have to do?

Thanks in advance!