John Aynsley, Doulos CTO will be presenting a FREE webinar on "VHDL versus SystemVerilog versus SystemC" on Friday 3 May 2013
There will be 2 sessions to enable attendees from different time zones:
1st run:
Time: 9am-10am (BST - UK) 
10am-11am (CEST) 1.30pm-2.30pm (IST)
2nd run:
Time: 9am-10am (PDT) 12pm-1pm (EDT) 5pm-6pm (BST - UK)
For further details and to register, please see the link on the Doulos website:
http://www.doulos.com/content/events/VHDL_vs_SV_vs_SC.php