Hello everyone,
I'm fairly new to the verification using UVM. I've watched a bunch of lectures about the UVM methodology from the MentorGraphics website, and implemented a simple UVM test for a simple FIFO I designed. Currently, this test has no configurability and that is the next step I'd like to take to get to know UVM better.
The FIFO is pretty simple, with 1 write and 1 read port, full and empty flags, and a reset. In my test all data and read/write flags are generated randomly, but I want to change that in order to be able to be me who says when to write, when to read and what to write.
am not very familiar with the concept of inheritance but I get the idea. Because of that, I haven't got any class that is extended from any of my own classes.
My question is where should I get started to add some configurability to the test?
Should I make several configuration classes and have general sequence/monitor/agent classes that get a configuration and do what they are supposed to by having big classes that interpret those configurations
OR
Should I have several smaller sequence/monitor/agent classes, each one doing a different thing, and have a simple configuration object indicate to the test which sequence/monitor/agent classes to override/use
OR
somehow a mix of both
Any suggestions or resources about configurability are welcome!