issue about read write-only register via backdoor

Hi all,

There is one register model such as this:

class R_r extends uvm_reg;
  uvm_reg_field     vaule;
  ...
endclass : R_r

class A_R_file extends uvm_reg_file;
  R_r     R;
  ...
endclass : A_R_file

class R_model extends uvm_reg_block;
  A_R_file     R_f;
  ...
endclass : R_model

class my_r_seq extends uvm_reg_sequence;
  R_model regmodel;
  ...
  write_reg(regmodel.R_f.R, status, wdata);
  peek_reg (regmodel.R_f.R, status, rdata);
  ...
endclass : my_r_seq

R_r is write-only, when reading R_r via backdoor as above, VCS reports such an error.