I'm trying to use the $past sampled value function, whose prototype is:
$past ( expression1 [, [number_of_ticks ] [, [expression2 ] [, [clocking_event]]] ] )
I've made a small example in which I use the 'expression2' argument:
module top;
bit clk;
logic enable;
logic [7:0] a;
always #1 clk = ~clk;
always @(posedge clk) begin
$display("past(a) = %x", $past(a, , enable));
end
initial begin
@(posedge clk);
enable <= 1;
a <= 'hf;
@(posedge clk);
enable <= 0;
a <= 'ha;
@(posedge clk);
@(posedge clk);
enable <= 1;
a <= 'h1;
@(posedge clk);
a <= 'h5;
@(posedge clk);
enable <= 0;
@(posedge clk);
@(posedge clk);
#1;
$finish();
end
endmodule
As per my understanding from the LRM (section 16.9.3), using 'enable' as the 'expression2' argument would mean that $past would use 'posedge clk iff enable' as a clocking event on which to sample past values. This means that this code snippet should only print out the non-gated values of 'a':
past(a) = xx past(a) = xx past(a) = 0f past(a) = 0f past(a) = 0f past(a) = 01 past(a) = 05 past(a) = 05
I've tried running this code on another simulator, though, and there I get a totally different printout:
past(a) = xx past(a) = xx past(a) = xx past(a) = xx past(a) = 0a past(a) = 01 past(a) = 01 past(a) = 01
Could some SystemVerilog guru please clarify which is the correct output and why?