Hi all,
I'm new with UVM and I came across a problem. I am working on an AXI RD VIP using UVM and I have the following issue.
In the data_phase (the data channel driving) from the MASTER driver, I need to drive the RREADY signal.
There are 3 handshake types described in the protocol specifications: valid before ready, ready before valid and ready and valid at the same time.
In case of valid before ready, I want to wait a certain number of clock cycles ( delay ) from the time that RVALID asserted and then to assert the RREADY signal.
From my understanding, all the delay information should come from the transaction(sequence_item).
The problem is that I generate a new transaction (sequence_item) with get_next_item only when I drive the address channel (in address_phase);
The data_phase works in parallel with the addr_phase and its independent of the address phase.
Also the data_phase needs multiple delay values (one for each data received from DUT, ex. arlen+1) while I only generate one transaction that contains the address channel informations.
Code example:
task run_phase(uvm_phase phase)
fork
forever begin
...
seq_item_port.get_next_item(req);
address_phase(req);
seq_item_port.item_done();
end
forever begin
data_phase();
end
endtask : run_phase
task address_phase(axi_item item);
// Drive the address channel
...
endtask : address_phase
task data_phase();
// Wait for the rvalid signal
while(!vif.rvalid) @(posedge vif.clk);
// Insert delay between rvalid assertion and rready assertion
repeat(<problem!!!!>) @(posedge vif.clk);
rready = 1;
...
endtask : data_phase
I don't know what variable (sequence_item variable) to set in the <problem!!!>
Can anyone give me an advice regarding this problem.
I repeat, I want all timing related data to be set from the sequence_item
Regards,
Adrian