multiple interfaces accessing the same uvm_reg

Multiple interfaces( processor 0 ,processor 1, processor 2) do write/read the same register.

I created p0_map, P1_map, P2_map and set different sequencers in environment.

regmodel.p0_map.set_sequencer(p0.sequencer,p0_reg2dm_adapter);

regmodel.p1_map.set_sequencer(p1.sequencer,p1_reg2dm_adapter);

regmodel.p2_map.set_sequencer(p2.sequencer,p2_reg2dm_adapter);

how i can map(by using add_submap) the same register block to p*_map.