When should we use uvm export
uvm_put_port is connected with uvm_put_imp. uvm_put_port will call put method which will be implemented in uvm_put_imp. My question is in which situation we use uvm_put_export
View ArticleHierarchical UVM Register Model and maps
Hi, I have a bus system with one master and upto 64 slaves. Each of the slaves has a register block, which is accessible by the bus master and a local SPI interface like this: +-----------+...
View ArticleAny DPI which can call Python in verilog testbench?
Hi, I am new to Python and I have been asked to build a UVM testbench which can call Python functions. Is there any way that I can do which is similar to DPI-C for C functions in verilog testbench?...
View ArticleIn-line random variable control
This section of the LRM is vague. 18.11 In-line random variable control What is the expected behavior for the following code? class child; rand int a; rand int b; constraint cb { a inside {[0:100]};...
View ArticleUser defines frontdoor sequence can't support simultaneous accesses
Hi We're trying to use a used defined frontdoor sequence for our register model. Most of our registers are accessed through an indirection mechanism, so creating a custom frontdoor sequence looks like...
View ArticleIs this UVM register model bug being address? UVM/RSRC/NOREGEX
Seen quite a few posts on various forums like this. Moving your register model to UVM-1.2 yields a bunch of warnings like this. [UVM/RSRC/NOREGEX] a resource with meta characters in the field name...
View ArticleIs clock information allow in C with UVM testbench using DPI?
Is clock(signal from rtl or from testbench) allow to be used in C program to trigger event or delay?
View ArticleDelay in UVM driver
Hi all, I'm new with UVM and I came across a problem. I am working on an AXI RD VIP using UVM and I have the following issue. In the data_phase (the data channel driving) from the MASTER driver, I...
View ArticleUVM Phases: end_of_elobration
I referred couple of documents; cookbook, uvm 1.2 user guide, to know why end_of_elobration is required. However, i could not find answers for 'why it is required' and more specifically 'Is it...
View Articlerandomize() with inside syntax
How can I use "randomize() with" along with "inside", on the same line? Below is some code that solves the problem using >= and <=, but I'd like to use "inside". module top; class aclass;...
View Articlemultiple interfaces accessing the same uvm_reg
Multiple interfaces( processor 0 ,processor 1, processor 2) do write/read the same register. I created p0_map, P1_map, P2_map and set different sequencers in environment....
View ArticleWhy doesn't this virtual interface connection crash and burn
Hi Everyone, I got some strange code (at least strange to me) from a college of mine and I can not understand why it works, reading the code I expect the tools to fail at compilation and elaboration...
View ArticleSVA for fairness of Round-Robin Arbiter
Are are any standard or recommended ways of verifying the functionality of the round-robin arbiter and more specifically checking the fairness? I'm looking for something that is scalable with the...
View Articlevirtual sequencer exit main phase prematurely
hi all, my SPI test stuck and test sequence is hung on wait_for_grant(). I turned the verbosity to UVM_DEBUG and found out virtual sequencer and physical sequencer exit from main phase and...
View ArticleIssue with add_hdl_path (peeking two sub modules regsiters)
HI I have two sub modules called A and B within DUT and trying to get register information of both A and B in back door using peek method. I have single ral block which includes both A and B...
View ArticleUsing DPI-C sin function
Hi, I'm trying to use DPI-C to import sin function, but it doesn't work, as a workround i had used a sin approximative function which finally give a static value of 2.5 (the offset value) i think...
View Articlepredictor / TLM model paradigm
What we've done in the past is have "phantom models" that are highly coupled with the RTL state machine. E.g. The RTL got a command, and performed: Read 0x1, Read 0x2, Write 0x1, Write 0x2. our...
View ArticleUse of intersection in cross coverpoints
I was under the assumption that once bins are created, the coverage would be collected only for those bins and the remaining combinations would be ignored. However, I noticed this was not the case when...
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Help regarding fork_join usage
Hi , Please help me the following code, module fork_join_any_process(); int me[3]; task automatic print_value; input [7:0] value; input [7:0] delay; begin $display("Waiting Passed value %d",value);...
View ArticleMultiple architectures - which one?
I am relatively new to UVM, and I'm trying to think through the architecture of a transaction. Assume that in this case, I have the ability to modify the object under discussion directly. I have a...
View ArticleGenerating constrained random pre-load file for SoC TB
Hi All, Any idea how to use UVM to generate a pre-load files using constrained random method for SoC verification. Is it OK to have an UVM agent for this purpose which does not require any...
View Articleread register from RAL
Hi, I have a question refer to strange messages created by RAL read command. When the register is read, I receive a message like: uvm_pkg::uvm_parent_child_link l103=config_dmaw_seq r107=transfer...
View ArticleControlling timescale with set_timeout
What is the recommended way to control the timescale of the UVM timeout as set with set_timeout()? Controlling the timescale in the calling code doesn't seem to work. For example, `timescale...
View Articlereal port mappping
Hi all, i'm tryin to make a SV code with the following bloks: -Gaussian nois generator: the output is 16 bit, but i had converted it to real ( i had just putted real in place of STD_logic) -Low pass...
View ArticleUVM RAL - Register Verification for Different Access types
I'm experimenting UVM RAL register verification for all the access types for registers and I'm experiencing the issue while using built-in sequence uvm_reg_access_seq. In my design I've implemented all...
View Articlehandle to uvm_component in uvm_object
Hi, Is there a way to avoid the "complex type usage" error when needing to feed a uvm_object a handle to an uvm_component? What I need to do is access within a sequence a method of one component in...
View Articlebuild_phase order
Hi, I notice something interesting in the build_phase order of uvm_component. The uvm_component at the same level are build in the alphabetatical order of the instance name. I expect the build order...
View Articleconfig_db usage: base class versus derived class objects
Is it possible to do a uvm_config_db::set() for an object of derived class type using the base class handle and later do a uvm_config_db::get() of same object using the derived class handle...
View ArticleIs it possible to have two implementation of b_transport?
I need to have two uvm_tlm_target_socket in a class and I need to do different set of things with the data received via two sockets. I was thinking if it is possible to have two implementation of...
View Articlenon-uvm message compliant, grep during report pahse.
is there way to search for the non-uvm compliant error message such as "ERROR - CSI Rx BFM " during the uvm report pahse of uvm environment? if we see this string error count variable need to be...
View ArticleUnique array elements without rand or randc
I have a variable logic [31:0] id which is not declared as rand or randc. I need different id's each time into an array logic [31:0] id_array [16].logic [31:0] id;logic [31:0] id_array...
View ArticleUVM Sequencer base class - Virtual task using local class variables - bad...
I see uvm_sequencer_base::wait_for_grant (UVM 1.1d) is a virtual task but accesses a local int g_request_id - is this not a bad coding style? If I were to override this virtual method for debug with...
View ArticleTurn off `uvm_info messages
Is there any way to turn off `uvm_info messages being displayed on the log while retaining `uvm_error and `uvm_fatal messages
View Articlemultiple maps on ral class
Hi, We are using snps ralgen to generate the regmodel. It appears that the ralgen creates only the default map. We would like to have 2 maps for 2 separated if masters. Is there an online example for...
View ArticleCommunication between uvm_sequence and uvm_component
I have two classes, one is block_seq which extends from uvm_sequence and other is block_cfg_mngr which extends from uvm_component. How do I exchange information between these two. I need to generate...
View Articlepriority for uvm_reg transactions
There are many threads/virtual sequences in the test that will initiate register transactions through a shared register model/bus agent. I want to give specific sequences higher priority so they will...
View ArticleHow to check VCS version number?
How can I check which VCS version I am using, from a Linux command line? I don't want to run a sim to find this information. I am looking for smthg like "irun -version", but for VCS. Pre-post...
View ArticleRAL mapping reg_field to another reg_field
Hey! I'm think need some help with RAL. I have 2 registers and in reg A field F1(RO) mapped from reg B field F1(RW) how i must implement this using RAL?
View ArticlePractical UVM Book now available.
Hello: After multiple years in development, I would like to announce my book Practical UVM. Practical UVM is a book that goes through a deep dive of the Universal Verification Methodology. In...
View ArticleUsage of get_hdl_path() for backdoor register access
Hi All, I wanted to know the usage of get_hdl_path() and get_full_hdl_path(). Any example would be helpful. I have added set_hdl_path_root for register block on top level and added add_hdl_path for...
View Articlewaiting for next clk edge, interfaces and clocking blocks
Q1) I'd like confirmation that the following waits for a posedge of clk are identical. (The code it refers to is far below.) 1) @(posedge my_play_if.clock); or @(posedge clk); 2)...
View ArticleImproving transaction recording
I am trying to improve transaction recording. So far we have used field automation macros, but to make debugging efficient I am trying to customize the recording. I've understood that the do_record...
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block level verification in a system setting
Let's say I have the following DUT. The UVM environment contains a chain of models/predictors. Input data flows down this chain and generates the expected CHIP output, which is compared to actual....
View ArticleQuery related to UVM_RAL_REG model.
I have query related to UVM_RAL model. Does it support for case-insensitive for accessing Registers and Register fields items from UVM_RAL model? For example. We have testcase with extension of...
View Articlestring literal spanning a newline (using a backslash) - vendor supported?
A backslash can be used to extend a string literal onto the next line if "the new line is immediately preceded by a \ (backslash)." Section 5.9 of 1800-2012.pdf, the SystemVerilog LRM I don't...
View ArticleWhat is a proper way to set fields and update register in uvm register model?
In my test sequence, some fields of a register are changed frequently and others are keep previous value. I wrote the code like below, register.fieldY.set(value) register.update(status) // first...
View ArticleInstance override RAL adapter transaction objects?
Hello, We have a test bench environment where we have 2 objects of the same SPI env class. The SPI env sets the sequencer for the RAL model as follows:...
View ArticleWhy we get SEQREQZMB when jumping to another phase
I have a reset sequence, which starts as default_sequence for reset_phase. For main_phase I have some sequence, which is started as default sequence. At some time I jump from main_phase to reset_phase....
View ArticleComplicated Register Modeling with uvm_reg
Looking for suggestions on the best approach to modeling something akin the following. data bus width: 16 bits addr bus width: 16 bits register: cfg @ 0xa000 field: value_mode @ 0 : enum {...
View ArticleAre there any recommendations/guidelines on using UVM run sub phases?
The cook book from Mentor tells following and in another thread, the moderator also suggested against using the sub phases of run. However in one of my projects, I do find the need for using them (and...
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