problem about configuring sub-sequencers of virtual sequencer using...
Hi, all, I met one problem when i configure sub-sequencers of virtual sequencer using uvm_config_db. Here are the codes and VCS reports: -------codes------- class my_subenv extends uvm_env; ......
View Articlehow to unpack payload?
Hello all, I am stuck at one place. I want to unpack my payload bytes which are actually produced by dynamic array. Some uvm geeks suggested me to use another parameter,length, in order to unpack the...
View ArticleHow to access fields within registers with the same name
The issue I have is the register model has multiple registers of different names but the fields within the registers are named the same. The register model is generated by a tool so getting changes...
View ArticleRegister read via register model.
I am reading a register with using uvm_reg method read_reg. so while doing this read transaction is happening on to the actual bus through agent ,but the I am not getting read value in read_reg task...
View ArticleVCS problem with SystemVerilog
Hi，experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error，but run time...
View ArticleVCS problem with SystemVerilog
Hi，experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error，but run time...
View ArticleHow virtual sequence start?
Hi all, I have ran into the problem about virual sequence's starting Here are the codes: class my_env extends uvm_env; ... master_vsequence v_seq[]; ... function void build_phase(uvm_phase phase);...
View ArticleHow to use a variable defined in one class into another class?
Hello all, Can A variable defined and used in one task, in one class, be used as it is in another class?But these two classes are completely independent of each other,in other words, they are not...
View Articleuvm_reg write semaphore
Hello,Inside uvm_reg there is a semaphore called m_atomic.This semaphore protect from write/read from several registers at the same time.I have a sequence that sends an item with write_reg task.When...
View ArticleHelp in resolving this error?
Hello all UVM geeks, I am getting the following error. Error: monitor71.sv(69): The actual (dataout) and formal (bytestream) for a ref must be equivalent types. Can someone please help me in...
View ArticleOVM RGM Porting to UVM
Hi, For the next project we are porting our methodology to UVM. I have one basic question, whether UVM supports RGM or it is completely RAL now?? Also is RAL supported by Cadence?? Thanks a lot,...
View ArticlePipelined RAL access
I am using UVM RAL (version 1.1c) and with my bus agent which supports pipelined requests and out of order responses. In RAL adapter I have set provides_responses=1. Now when I have two read requests...
View ArticleReturn from function to pass into another function?
Hello all, I want to pass the output of one function (10b8b decoder) into the input of another function viz. drive, where in drive function, I am creating the array out of each byte received from...
View ArticleProblem when setting breakpoint using ucli
Hi, experts, I want to set one breakpoint in the specific line in the specific file. But the ucli reports such an error: ucli% stop -line 1371 -file uvm_reg_field.sv...
View Articleproblem about macro uvm_do_with()
Hi, all I have met such a problem, when i use uvm_do_with to start item, then it is stuck at uvm_do_with. The hierarchy struct of the sequence is v_seq |- cfg_seq |- sub_seq |-...
View ArticleOut of bound error in UVM 1.1c
Hi there, While migrating from UVM 1.1a to UVM 1.1c, below error flashes: Error Out of bound access /uvm-1.1c/src/base/uvm_misc.svh, 273 Out of bound access on smart queue (size:0, index:-1)...
View Articleproblem about uvm_config_db
Hi all, Usually we use uvm_config_db::set from the higher hierarchy module and uvm_config_db::get in the lower hierarchy module, Can we use uvm_config_db::set and uvm_config_db::get from the opposite...
View ArticleHow to pass variable sized packed arguments to a task/function?
In SystemVerilog we can have dynamic unpacked arrays and they can be passed to a function/task. I was wondering if there is a way to pass dynamic packed arrays to a function/task. For example consider...
View ArticleHow to pass register model for in-built sequence??
Hi, I have created a basic test for register testing. I am using the in-built register sequence i.e. uvm_reg_hw_reset_seq. But I was wondering how to pass my register model to this sequence, as...
View Articleproblem about variable part select in SystemVerilog
Hi all, I have one problem about variable part select of Verilog. If you know the width, but the upper or lower range is a variable, you can use variable part select. eg : addr[idx_bits-:8] =...
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