problem about variable part select in SystemVerilog

Hi all,

I have one problem about variable part select of Verilog. If you know the width, but the upper or lower range is a variable, you can use variable part select.

eg : 

addr[idx_bits-:8] = {8{1'b1}}; 

t's okay.

But if you know the upper or lower range, the width is a variable, how can you do? I adapt the similar way of variable part select.

eg: 

addr[8-:idx_bits] = {idx_bits{1'b1}};

VCS reports such an error: