Hello,
The question is SystemVerilog specific, not related to UVM. I was wondering if it is possible to initialize an interface inside an internal module A and further pass it to an another module B, which is at the same level of hierarchy as the module A.
interface Inter (input logic clk); logic a; endinterface module A(Inter inter); logic clk; Inter inter(clk); endmodule module B(Inter inter); always_ff @(posedge inter.clk) ..... endmodule module top; A a( .* ); B b( .* ); endmodule
Let's assume module A is a master of some Stream interface (like AXI4-Stream), B is the slave. The signal clk could be a regular variable inside the Inter, however, clk must be connected to the interface, so it seems logical to me, that it's on the port list, so developer will not forget to provide it. Therefore (port assignment of inter), the inter has to be initialized inside the module A, not in top as it would be done in case of regular interface usage. The code is for synthesis and my compiler doesn't support virtual interfaces. Does it exist any elegant solution for the described issue ?
Thanks,
Adrian