uvm component name constraints
We've been using UVM 1.1d. Now we're testing 1.2 and after cleaning up some other things we're getting warnings like this:the name "sso_aw_tb_top.sso_aw_wrapper_i.sso_aw.aw_csr.aq.aq_thr_port" of the...
View ArticleHow to monitor DUT outputs from a test/sequence?
I am learning UVM. So far I was able to create the following environment for my DUT. Agents with monitors, drivers and sequences for all of the input-output interfaces from my DUT. A top level UVM env....
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Cross coverage of two covergroups
Hi Everyone, I am using the UVM env, in that I have two agents lets say agent1 and agen2, I want to get the cross coverage of input stimulus generated by both agents. What I did till now , I have a...
View ArticleHow can I upgrade all `uvm_error to be `uvm_fatal ?
What is the easiest way to get my simulation to die upon reaching the first UVM_ERROR? (I suppose the reporting class could be extended and overridden, or something like that, but if it gets too...
View ArticleCadence: Incisive Enterprise Simulator vs. Incisive Unified Simulator -...
Q1) What is the difference between Incisive Enterprise Simulator (IES) and Incisive Unified Simulator (IUS)? Q2) If you are from Cadence (or even if you are not), how can I easily find this...
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run_test
On page 6, of the UVM User's Guide, http://www.accellera.org/downloads/standards/uvm/uvm_users_guide_1.1.pdf, run_test is shown as a method of uvm_env. Yet in...
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Passing sequence_items from v-sequence to sub-sequence?
Is there a way for a virtual sequence to pass a sequence_item (that it has already created) to a sub-sequence, say for instance to an agent sequence, without using a TLM? I really would like to avoid...
View ArticleRegarding multiple reset test
Hi, I am implementing multiple reset inside UVC componenets (sequencer, driver, monitor and etc). When reset is asserted between get_next_item() and item_done(), the following error is issued....
View Articleuvm_vreg increment issues
I am working an a block that requires two different type of buffer descriptors, let call them bd_base, bd_ext.bd_base is size 8 bytes and bd_ext is size 32 bytes. These are implemented on a 64 bit (8...
View Article+uvm_set_default_sequence usage behavior in UVM 1.2
I have two sequences seq_a and seq_b that can be run on sequencer. In my component i have the code to set the default sequence. Below is the code in component and i am trying to set the default...
View Article+uvm_set_default_sequence=*,run_phase is causing two threads to spawn
I am running the UVM 1.2 examples code given in following link, which are there to demonstrate the UVM 1.2 new features. http://www.edaplayground.com/s/4/1037 In the above code, the default...
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Many-to-one on a TLM
Rookie question: Is it as obvious as it may seem to simply have just the one imp on the consumer side of say a put_port (non-blocking most likely), and multiple producers can connect to that single...
View Articlefixed-size arrays : Do they not 'support' size()?
Do fixed-size arrays not support .size()? Or, am I doing smthg wrong below? Running irun 13.1, I am told that .size() "is not a valid built in method name for this object". If they do not, is...
View ArticleThe difference between run_phase and main_phase in uvm_component
Hi, Could anyone please clarify what's the difference between run_phase and main_phase in uvm_component? What are both do for? Thanks, Brian
View Articleoverriding a registered local variable in a sequence from test
Following is the example class my_sequence extends uvm_sequence... string file_name; `uvm_object_utils_begin(mysequence) `uvm_field_string(file_name,UVM_DEFAULT) `uvm_object_utils_end endclass...
View Articleinterfaces initialization inside internal module
Hello, The question is SystemVerilog specific, not related to UVM. I was wondering if it is possible to initialize an interface inside an internal module A and further pass it to an another module B,...
View ArticleUVM 1.1d in QuestaSim with -pedanticerrors
Hi, I've tried compiling UVM with QuestaSim and the switch "-pedanticerrors" but it complains in the file uvm_component.svh that virtual method calls are not allowed in the constructor because it can...
View Articleuvm_re_match
Hi all, I am facing a "UVM_ERROR:uvm_re_match" while using incisiv-10.20.030 What can be done to resolve this issue? Thank you Love
View Article`uvm_do_with is not working with variable constraint
Following is the sequence code class basic_sequence extends from uvm_sequence(#sequence_item); sequence_item item; task body() fp1 =fscanf("abc.txt", addr, data); `uvm_do_with(item,{...
View ArticleHandling protocol extensions
Hi everyone, I'm curious how you handle extensions to a protocol UVC. Let's say we have an APB UVC that implements the AMBA protocol. Let's also say that we have a DUT that, aside from the signals...
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