Hi,
I am using UVM heartbeat in my testbench and defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, so the run time phase will be of type 'uvm_callbacks_objection' instead of 'uvm_objection'.
In order to do some end of sim checks, i am waiting for 'phase.wait_for_state(UVM_PHASE_READY_TO_END, UVM_EQ);'
Looks like the phase's state is not changing to 'UVM_PHASE_DONE', it is still 'UVM_PHASE_EXECUTING'. The total objection count is 0.
During this time, heartbeat event is getting triggered and test is ending with a fatal msg, which is not expected.
Configured Hearbeat mode = UVM_ANY_ACTIVE.
Heartbeat_window = 100000;;
Snippet from log:
The total objection count is 0
Heartbeat : Triggering an heart beat event at T= 190624 ns
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The total objection count is 0
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