SystemVerilog connecting a channel
I'm trying to hook up a new channel (channel 2) to an existing one (channel1) like so:channel channel1;channel channel2;extern function new(channel_type channel2);function subenv1::new(channel...
View ArticleRnadomize a variable inside a function
Hi, I want to randomize a variable defined in a function. The function is inside a package. I tried declaring a class inside the package and taking the instance of that class in the function. But...
View Articleverifying protocol without reference model
I am new to verification. Now I trying to verify a protocol like TCP/IP stack(mainly TCP over IP, without UDP, ICMP etc.). My first idea is that a golden Reference Model is needed. I generate...
View ArticleUVM_REG and multiple reset
Hi, I am testing multiple reset. My testbench is based on UVM_REG and I am using "write()" API to write registers. If reset is asserted when write() is executed, the next warning occurs....
View ArticleRegarding the UVM field automation macros
Hi, We are planning to use UVM for full chip level verification. Some of the papers and posts recommending against the usage of field automation macros. Are these macros improved in latest version of...
View ArticlePseudo timing checks in UVC
Hi everyone, I have a question that is more on the methodology side. Let me describe the issue. For our APB peripherals we have a little deviation from the standard protocol. The protocol mentions...
View ArticleUVM Heartbeat: How does it works?
Hi, I am using UVM heartbeat in my testbench and defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, so the run time phase will be of type 'uvm_callbacks_objection' instead of 'uvm_objection'. In...
View ArticleUsing $past in procedural code
Hi everyone, I'm not sure if this is the right place to post this. I have question regarding the usage of $past(...) and the other members of that family inside procedural code. The SV 2012 standard...
View ArticleRandomization in an initial block
I have a module defined as follows... module dut(); int i; initial begin i = $urandom_range(0, 500); $display("The value of i is %1d", i); end endmodule // dut I'm trying to...
View ArticleSV & UVM June Training in Irvine & San Diego by Cliff Cummings
Cliff Cummings, President of Sunburst Design, will be conducting 2-day SystemVerilog / 3-day UVM Verification training in Irvine, CA - June 9-13, and in San Diego, CA - June 16-20. See the...
View Articlehow to drive a clocking block output asynchronously
Our uvm_driver derivatives push values into the RTL via clocking blocks in interfaces. This updates the signals synchronously as we typically want, but is there a recommended way to add an...
View Articleuvm_analysis_imp#()::get would be nice
It would be really nice to be able to receive TLM messages in some sequences for the purposes of coordinating stimulus with monitored events. I have a solution which gets the job done, but it's not...
View Articleassert(std::randomize(variable)) when assertions are turned off
What systemverilog standard defines when we use assert(std::randomize(variable)) when assertions are turned off I am using it but bit confuse what should simulators do ? will it still randomize...
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Can't record dynamic array in sequence item in QuestaSim 10.3a_1
I am using QuestaSim 10.3a_1 and try to record a dynamic array in the sequence item. But it doesn't show in the waveform window. When I try to fix the array size and use uvm_field_sarray_int to record...
View ArticleHow to delay a sequence from a test
Hi, I have a sequence running but i want to delay that sequence for 50 clk. How can i do it from the test. Is reset_phase a good option in the test class? or is their another way out. thanks
View ArticleAccessing Memory model from various sequences
I need to use a common memory for 2 sequences. I have a memory defined as uvm_component and all the logic needed to build a memory and its parameterizable. This memory is placed in the sequencer so...
View ArticleDifference between RAL and RGM?
Hi, I have a doubt related to UVM 's RAL with compared to OVM's RGM. The OVM's RGM seems to have only two sets of registers i.e., the actual ones belonging to DUT and the other belonging to the...
View ArticleHow to only create a dynamic array and not do randomize on 'rand int a[ ]' in...
I have a dynamic array in sequence item as below: rand int array_size; rand int a []; constraint c_order {solve array_size before a;}; constraint c_size { a.size() == array_size;}; In some...
View ArticleRunning testcase in Questasim
Hi all, I tried to run a testcase ( test_write_sequence) using command line in Questasim... I had coded a AHB UVC and wanna to perform a simple write transaction.. But the tool called $finish in...
View Articlerun time issue questa sim
I ran a testcase using questa sim,i am getting following output. ** Error: (vsim-3601) Iteration limit reached at time 0 ps testcase run phase look like this. it printed info messages from...
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