constraining sub-sequences in a virtual sequence - best practice?

Say I have these sequences:

class cfg_seq extends uvm_sequence #(obj_type1);
  `uvm_object_utils(cfg_seq)
  rand int unsigned size_x;
  rand int unsigned size_y;
...
  task body;
    //Generate objects based on size_x and size_y
  endtask
endclass

class item_seq extends uvm_sequence #(obj_type2);
  `uvm_object_utils(cfg_seq)
  rand int unsigned size_x;
  rand int unsigned size_y;
...
  task body;
    //Generate objects based on size_x and size_y
  endtask
endclass

I want to use them in a virtual sequence like this:

class test_vseq extends uvm_sequence;
  `uvm_declare_p_sequencer(some_vseqr)
  `uvm_object_utils(test_vseq)

  rand int unsigned size_x;
  rand int unsigned size_y;

  rand cfg_seq cfg;
  rand item_seq item;

  //This is what I'm trying to achieve
  constraint size_c {
    cfg.size_x == this.size_x;
    cfg.size_y == this.size_y;
    item.size_x == this.size_x;
    item.size_y == this.size_y;
  }
...
  task body;
    `uvm_do_on(cfg, p_sequencer.cfg_seqr)
    `uvm_do_on(item, p_sequencer.item_seqr)
  endtask
endclass

What I'm trying to do is that I set "size_x" and "size_y" in test_vseq and have cfg and item pick it up from test_vseq, so I don't have to set them separately in config_db. What's the best way to do this?