Hi All,
I am using system verilog constraints framework to randomize bunch of registers for my design. Each register has few register fields & all of them are declared as a 'rand' variables.
In below case, in my original source-code of constraints, I have declared ABC as 'rand' variable along with XYZ variable. However, when the constraints are getting solved, at the state of failure, ABC is given a value of 1'h1. even though my source code says,
'solve Reg1.XYZ before Reg2.ABC'
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Source-code:
----
solve Reg1.XYZ before Reg2.ABC;
Reg1.XYZ.value == 0;
if(Reg1.XYZ.value == 0) Reg2.ABC.value == 0;
----
Error::
-------
Solver failed when solving following set of constraints
bit[0:0] Reg2.ABC.value = 1'h1;
rand bit[1:0] Reg1.XYZ.value; // rand_mode = ON
constraint c_RandomizeReg2.ABCType // (from (constraint_mode = ON) (rndcfg_constraints_def_gen.sv:3063)
{
(Reg1.XYZ.value == 2'h0);
(Reg1.XYZ.value == 2'h0) -> (Reg2.ABC.value == 1'h0);
}
-----------
In the above failure, what I am confused about is that why is VCS fixing value of Reg2.ABC set to 1'h1 when value of Reg1.XYZ is not yet assigned even though I have a line which says 'solve .. before ...'
I am using below VCS version:
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Chronologic VCS simulator copyright 1991-2013
Contains Synopsys proprietary information.
Compiler version H-2013.06-SP1-10; Runtime version H-2013.06-SP1-10; Dec 4 13:48 2014
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I don't have any hardcoding done in my code which forces ABC to be value of 1.
Another observation I made is, if I do a command-line force of ABC register field to be value of '0', it will pass the constraint as expected giving me the intended result. However when I let the simulator pick the value, it doesn't solve the constraint.
Can someone please throw light on how can I go about debugging why is the simulator setting the value of ABC & not honoring solve-before.
thanks,
-Rashmi