SC_FIXED and UVM ML Packer
Hi, I am trying to use SC_FIXED in a UVM ML environment, but the uvm_packer.h doesn't support sc_fixed. virtual uvm_packer& operator << (bool a); virtual uvm_packer& operator <<...
View Articleworkaround to control register write order for wide fields
In the UVM register model, if you create a register or a field which is wider than the bus width there is no way to control what order the multiple bus operations occur to update the register/field...
View ArticleHow to get virtual interface in sequence
HI Can any one provide some example for how to get virtual interface in sequence? I need to use the clk in sequece . Thanks praneeth
View ArticleUVM-REG Built-in Frontdoor and Bus byte enables computation issue?
Hi, While debugging a prediction error returned by "Bit Bashing Test Sequence", I came to read the uvm_reg_map::do_bus_read/do_bus_write methods which seems incorrect when it comes to computing the...
View ArticleParameterized interfaces
a usual way to do it is to create a wrapper object and push the wrapper into config_db. Then get this wrapper object from config_db and assign it to the virtual interface pointer (not mentioning the...
View Articleuvm_resource_db usage
Hi, I am using uvm_resource_db to set and get any component configuration. But I am getting an error saying configuration object is not found. Its something that its not able to get the config object...
View ArticleNeed ncsim startup steps.
Hello Team, I am new to the cadence tool and using ncsim 10.2. I have to compile and simulate the .SV and uvm environment. Please suggest steps for running the ncsim for the first time. The error i...
View Articlemember reference resolution error related to uvm_analysis_imp_decl
Hi, I am seeing member reference resolution error related to uvm_analysis_imp_decl. Linenum52:`uvm_analysis_imp_decl(_mon).Please see in below code. You can see the error as well below which got...
View Articleusing uvm_config_db::get inside a module
Hi, can i use uvm_config_db::get function from inside a module? i want to create a configuration object in the test, set it at the config_db and get it in a VIP written as a module. something like...
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uvm object into uvm sequence
Hi, I actually want to write a very simple sequence that use a variable of class extends uvm object type. So I firstly wrote a small class extends uvm object that contains all the properties I want...
View ArticleUVM_REG post_predict(...) for registers
Is there any particular reason why uvm_reg doesn't have an associated post_predict function or post_predict callbacks defined? A use model could be, for example, to check bus responses of register...
View Articlehow to use uvm reg callback to implement reg_a read being qualified by a...
Hi, I have implemented a uvm reg block containing several uvm reg's. What I want to model is register reg_a has the following layout: {fld_a, fld_b,fld_c} and register reg_b has: {fld_st,fld_rsv} The...
View Articleiff usage (as a mechanism for waiting)
I happened across the following code. @(m_vif.smp_cb iff (m_vif.smp_cb.xyz_enable) ); To get to the crux of my question, let's consider it to be the below code. I don't think I've dropped anything...
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