`uvm_do_with
Does `uvm_do_with(REQ, CNST) take into considiration the default constraints in the class defenition ? From what I see it ignores those constaints. If so is there a way to solve this ?
View ArticleHow to generate the even number's and add number's.
Hi all, I have 16 bit data line and in transaction class i declared as "rand". But i want even even number's in one transaction and odd no number's in another transaction. Please suggests me.. Regards,...
View Articleuvm_config_db multiple instances
In the env, there is such uvm_config_db::set(): for (int i = 0; i < host_num; i++) begin inst_name = $sformatf("*.v_seq.slv_seq[%0d]", i); uvm_config_db#(uvm_event)::set(uvm_root::get(), inst_name,...
View ArticleHow to send some random data in between two packets/frames?
Dear All, I need to send some high impedance/IDLE symbols (eg 101010...) between the two packets/frames for long time. So is it possible in UVM to send some random data (not through packets in the...
View ArticleHow to create custom report severity
What is best way to override default uvm severity types (UVM_INFO, UVM_ERROR, UVM_WARNING, UVM_FATAL) with custom report severity types. For example, instead of displaying : UVM_INFO @ 0: reporter...
View Articleuvm_cmdline_processor get_arg_value/s to receive hex
SPOILER ALERT: I figured this one out, but since I'd already typed up most of the question, here it is anyhow posted to the public domain. Comments welcome....
View ArticleStarting multiple sequence in one phase
Hi, Is it possible to configure multiple sequences in one phase for one sequencer? Like i have multiple sequencers in my env. In one of the sequencer main pahse i am registering default sequnce as...
View ArticleAXI Bridge to ethernet connection
Hi, I've created a UVM model for ethernet 10Gb MAC CoRE. There is a requirement to connect the AXI Bridge to my UVM model. I'm facing severe problems while integrating AXI Bridge to ethernet model....
View Articlesequence/driver response scheme improvement
When a driver returns a response to the sequence, it calls 'set_id_info()' to set the identifiers of the transactions returned. This way, the originating sequence can correlate the response and the...
View ArticleHow to Use multiple lower layer sequencers in parallel
In the Layered Sequencers, As shown in the figure below, I want to use multiple lower layer sequencers(1,2,3) in parallel. Is it possible? If possible, Can you tell me how do I implement?...
View ArticleUVM simulation phases
Hi, I have created pre_reset and pre_configure phase in my test. I have not registered any sequence for pre_reset and pre_configure phase but I have some delay in my pre_reset phase of the test....
View ArticleHow to create different phase domain?
Hi, UVM Exports, I am writing a test to put 2 uvm_env A and B together and hope to separate them in different domains. I hope to give each environment his own run_phases time line. how could I do...
View ArticleSystemVerilog checkers. simulator support. usage in a UVM environment
Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the...
View Articlebug in uvm_reg_block - lock_model() function?
In the uvm_reg_block::lock_model() , there is a check for duplicate names of the reg block. This check uses get_name(). Shouldn't it be using get_full_name() ?? the error that results is :...
View Articlequestion about `uvm_sequence_utils
Does the latest uvm no longer have `uvm_sequence_utils? In the user_guide, seems `uvm_object_utils(seq) is enough to associate a sequence with a sequencer? how does it work? thanks,
View Articlesequence is not running - make sure sequencer name 'correct'
//This is not a question, but me storing some debug notes online, lest I run into this problem again. //good for debugging this issue, print_topology in particular. Put them in your test....
View ArticleInstance override of a parametrized type
I'm attempting to do an instance override on a parametrized type in UVM, but I can't seem to set a correct path to the instance I want to override. The code below...
View ArticleHow to Use Virtual Sequencers to Control Both Non-virtual Sub Sequencers and...
Hello Everyone, Good day. I am creating a testbench that has a structure shown below and am encountering errors perhaps due to the multi-layered virtual sequencer controlling both non-virtual sub...
View ArticleSystemverilog simulator
Can anybody shed any light on free systemverilog simulator? Thanks in Advance .. Ashish
View ArticleDoulos "First Steps with UVM" free multilingual webinar, Friday 2nd...
This free webinar will be presented in in English, French and German. To see further details and to register please visit: http://www.doulos.com/content/events/easierUVM_FirstSteps_English.php...
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