How to respond for a NACK request to resend the frame in UVM?
Hello all, How do I set priorities for some features, to be added in a transaction class? Is there any method in UVM for that? For eg. when I get a NACK, I need to respond to it quickly and resend...
View ArticleQuestasim simulation error?
Dear All, I am getting one strange error while using questasim 10.2a. While simulating 1st time, it simulates properly, all the packages, libraries get loaded fine. But when I tried to simulate the...
View ArticleHaving Power Aware and Performance verification component integrated
Hi All, I am new to UVM methodology. I have gone through UVM class reference manual. As, UVM is an open source method used by whole verification industry, Run time performance verification and power...
View ArticleNesting of frames in UVM?
Hello all, I want to create nested frames/packets. My packet structure is shown below. I want to have nested frames(one or more frames within another frame) starting from 2nd byte of header and...
View Articlewhy is uvm_void class need in uvm library
why do we have the base class as uvm_void in uvm library even though it doesn't have any variables or functions? what purpose does it serve?
View ArticleIncompatible complex type usage in uvm
Hi, In my current environment I have monitors class and parametrized scoreboard class. I am sending monitor transaction into scoreboard through the tlm analysis port. Below is snippet of code....
View ArticleQuestasim simulation error?
Dear All, I am getting one strange error while using questasim 10.2a. While simulating 1st time, it simulates properly, all the packages, libraries get loaded fine. But when I tried to simulate the...
View ArticleSwitching between data_items during simullation
Hi , I would like to use some data items in one test: frame_packet, short_packet , illegal_packet. In the uvm documentation i found that in order to switch between packets i should use factory...
View ArticleFree systemverilog/uvm simulator for small amounts of code exists?
Is there any free systemverilog simulator (w/ UVM support) for small amounts of code? i.e. perhaps a vendor offers the license for free, to hook newbies and students, restricting them to less than 1000...
View ArticleDoulos official training provider at DAC 2013
As part of the special 50th anniversary of the Design Automation Conference in Austin Texas, Doulos will present an entire day of world-class training, in four subject areas, on Thursday June 6 - Don't...
View ArticleStreaming operator for unpacking a bitstream
I'm stuck on a problem I encountered with a use of the streaming operator to unpack into a dynamic array. Rather than write procedural code, I thought I could use it actually with some amount of...
View ArticleProblem with uvm_object_utils
Hi All, I am getting following error message while using `uvm_object_utils to register a sequence : 1) m_do_cycle_check is not a class item 2) Expecting a function name 3)...
View Article3 TLMs between sequencer and driver?
Hello all, Can I have 3 TLMs connected between a single sequencer and a single driver in UVM? In other words, I want 3 pipes/TLM connections to send three different kind of packets to the same driver...
View Articleuvm_tlm_time not derived from uvm_object
Is there some reason uvm_tim_time is not derived from uvm_object? It contains just the sort of timescale neutral API I was looking for, so I added it to a class I'm developing. I'm not able to use...
View Articleconnection between monitor and driver?
Hello All, I need to send some bytes/packets(which are received from the DUT, for eg. NACK for missed packets) to the driver. So can I directly connect the monitor to the driver, without going through...
View Articlecontrol knobs for a driver to be controlled from test class?
Dear All, Is it always the case that the TOP test class can control/manage the control knobs of sequences only? I mean, I want to override/control some parameters of driver class from top test class,...
View ArticleIs it possible to call Python script from SystemVerilog?
Is there any way to call python function from SystemVerilog?
View ArticleUVMconnect: no field named m_get_if_mask
Hi all, I'm facing an issue when using the UVMconnect package. The simulator complains about missing fields: # ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm1.sv(652): No field...
View ArticleSingle transaction class to create different kinds of pkts?
Dear all, I need to create different kinds of packets, for eg nested packets(one or more pkts encapsulated in another pkt), simple packets etc, of the same protocol. Can these different kinds of pkts...
View ArticleMany more sequences in a single sequence?
Hello all, Can there be more than one different kinds of sequences, containing different kinds of pkts, be nested in one single sequence? so that the test case scenerio, will be to show different kinds...
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