parsing using system verilog

Hi,

I have an IP with built in tests, written in pyhton.

I want to parse those tests and use them in higher level (uvm testbench). Eventually each test will be a uvm sequence.

For that I need a system verilog parser.

Is there a reference that I can use for this purpose?

example for lines in existing test:

WriteBlock SLAVE 0x0000ffff

Data 8

a5a5a5a5 ffffffff 

Thanks