Connect interface to dut

Hi,

I have issues connecting my interface to my dut when using the cadence compilator (vcs does not give any warning here): See the source code below. I get the following warning:

ncelab: *W,ICDPAVW (<my_file>): Illegal combination of driver and procedural assignment to variable my_data detected (output clockvar found in clocking block at line <n> in file <my_file>).
           .out_data  (my_if.my_data)

Any idea what is wrong her?

Thank you

Here's the source code:

interface my_if (input bit clk);

  logic reset;
  logic data;

   clocking master_cb @ (posedge clk);
      output                data;
   endclocking // cb

   clocking slave_cb @ (posedge clk);
      input                data;
   endclocking // cb

   clocking passive_cb @ (posedge clk);
      input                data;
   endclocking // cb

endinterface : my_if

module tb_top;

   logic clk;
   logic reset;

   /* Dut interfaces */
   my_if my_if(clk);
  
   /* Clocks and reset gen*/
   <...>


   assign my_if.reset = reset;

   dut
     my_dut(
                 .clk      (my_if.clk),
                 .arst     (my_if.reset),
                 .out_data (my_if.data)
     );

   initial begin : ib_main
      <...>

   end

endmodule