UVM Phase issue
Hi UVM Experts, I am facing some issue with UVM phase. I have registered one sequence to pre_configure phase of one sequencer which is doing some chip configuration. In my base test pre_configure...
View ArticleUVM and SystemVerilog Papers at DVClub Sept 9
The DVClub meeting September 9 is 100% dedicated to you all reading this forum -- UVM and SystemVerilog. We'll have four topics in this fast-moving event: Update from the Accellera UVM Working Group...
View ArticleVCS: uvm config db with array of interface
Hi, Is there limitations when using uvm_config_db with interface array: Here is an example where I get compilation error: module tb_top(); import uvm_pkg::*; /* DUT interfaces */ test_if...
View Articleparsing using system verilog
Hi, I have an IP with built in tests, written in pyhton. I want to parse those tests and use them in higher level (uvm testbench). Eventually each test will be a uvm sequence. For that I need a system...
View ArticleConnect interface to dut
Hi, I have issues connecting my interface to my dut when using the cadence compilator (vcs does not give any warning here): See the source code below. I get the following warning: ncelab:...
View ArticleAuto-generate doc script, UVM to HTML
Hi, I have a question regarding Auto-generate doc script, UVM to HTML: We're in a process of defining UVM coding guidelines in our group. We would like to guide engineers to write code and comments in...
View ArticleSigned field in RAL model
Hello All, I have some queries regarding RAL model : (1.) How to declare any particular Register's filed as "signed" in RAL model? (2.) By default all the register fields in RAL model are...
View ArticleOf begin_event, end_event, transaction recording, and pipelined interfaces
What is the proper use of begin_tr() and end_tr() and their associated events? There are these very nice descriptions for begin_event and end_event. // Variable: begin_event // // A...
View Articleuvm_do_with constrain problem with sequence
class my_transaction extends uvm_sequence_item; .... int a; int b; int c; .... endclass class my_sequence extends uvm_sequence#(..) .... my_transaction tx; ......
View ArticleUVM_FATAL invokes $finish(1)
To circumvent UVM calling on $finish directly when completing normally, one would override "finish_on_completion" to 0 before calling "run_test()". What I do is: uvm_top.finish_on_completion = 0;...
View ArticleWhat ever you do, don't use ...
I just saw a presentation on UVM tips and it recommended to NOT use the uvm_field macros. Several companies have come out and said that these generate large, cumbersome methods that are hard to debug,...
View ArticleMultiple CPU interfaces can access the same register model
Hi, Assuming my DUT has 2 external CPU interfaces that can access to the same Register Model. How should I implement it in my UVM environment ? I guess I need 2 adapters and 2 predictors. Do I need...
View ArticleScoreboarding the Register Model
I am attempting to implement the UVM register model in my testbenches. Are there reference implementations that connect to a scoreboard? Our methodology uses C++ reference models with fields identical...
View ArticleControlling verbosity while using component override
Hi, My question is about controlling the verbosity for one agent when I am using override for it. Let me give more details here. I have base env and base agent class. My environment extends this...
View ArticleRegister "abc_rm.mem" value read from DUT (0x0000000000000002) does...
Can any one please explain what this would mean . I can write on the this register perfectly . The only problem is reading . I am performing uvm_reg_single_bit_bash_seq on this register .
View Articleconnect uvm_analysis_export (SV) and tlm_aanalysis_port (SC) with UVMC
Hi, I am trying to connect uvm_analysis_export (SV) and tlm_aanalysis_port (SC) using UVMC like the following: uvm_analysis_export #(obs_xact#(WL,DEP)) sc_export;...
View ArticleProblem in viewing waveform
Hi All, I am using Cadence ncsim. I have an (UVM Verification Component)UVC which is not connected to any DUT for now. It is a simple UVC which just generates few address,Data and READ or WRITE...
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how to (best) delay the start of built-in UVM register test stimulus
I've run into the following issue using the built-in UVM register tests. The built-in UVM register tests (seem to) start R/W-ing immediately after top-level reset is released. This was fine,...
View ArticleHow inputs are driven in UVM ?
Hello, I'm newbie to UVM. I'm trying to develop a 2:1 Mux using UVM standard classs libraries. I've a question that how the inputs are generated using Sequences and driven at driver side to interface ?...
View ArticleDisable UVM_INFO printout by verbosity
Hello, I have a library with the sequence which exploits `uvm_info to print messages. It uses UVM_MEDIUM verbosity and AXI4STREAM_SLAVE id. I would like to disable those messages, however I can't...
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