UVM test simulation using vcs and DVE

Hi,

I am a beginner ..

I wrote a simple UVM verification environment using the uvm-1.2 examples, and could compile and run it but I could not see any wave form.

the run command : simv +UVM_STACKRACE +UVM_TESTNAME=test_base -l run.log -gui

in the run.log I could see that the simulation time is 1000ps

how can I see the waveform (want to check if the clock and reset signals were correctly operated)???

thanks a lot