reset_phase to be obsolete soon ?
Hello there, As per Mentor's UVM guidelines 5.2 [1], reset_phase() will be obsolete in future releases. During DVCon 2014, Cadence recommends to use run_phases() on slide 5 of [2]. With the release...
View ArticleUVM test simulation using vcs and DVE
Hi, I am a beginner .. I wrote a simple UVM verification environment using the uvm-1.2 examples, and could compile and run it but I could not see any wave form. the run command : simv +UVM_STACKRACE...
View Articleproblem with uvm ral read/mirror
Hi, I am having some trouble with creating a register model for my DUT. It is intended for APB transactions. I included an adapter and a predictor. When i try to read or mirror a register i have...
View Articledeprecated code in uvm
I have a question concerning the use of deprecated code in the uvm. There are a number of features that are "deprecated", and the user can exclude them with UVM_NO_DEPRECATED. The library states that...
View Article`uvm_*_utils macros useful in virtual class extended from uvm_object?
Does an abstract class (virtual class ....), which extends from uvm_object, benefit from using uvm utility macros (`uvm_component_utils, `uvm_object_utils)? As I understand, `uvm_component_utils and...
View Articleuvm sequence
Which is best method to start , randomize and end the sequence among the `uvm_do, start_item, `uvm_create, `uvm_send and the others and why? Please explain.
View ArticlePackage in SystemVerilog
Hi All, I have to access the associative array declared in top module from one of the TB files. All TB files are part of the package which is imported in the top module. When i am trying to access...
View ArticleDifferent packet types with single sequencer.?
Hi, Here I am attaching a sample code for my doubt: 1) class base_pkt extends uvm_sequence_items; - - endclass 2) class base1_pkt extends base_pkt; - - endclass...
View ArticleDUT Model synchronization
Let's say that I have a VHDL DUT which is a state machine driven by a 50MHz clock (20 ns period). This state machine has 5 states which advance on every clock, and loops after the final state. On the...
View ArticleTCL in RivieraPro
Does anyone know how to display the pathname of the currently running script in RivieraPro? Note** This is when executing the script using the "Do" Command (Gear icon), not the "source" command. aka...
View ArticleCompiling UV
I bought a couple of books on UVM and am intrigued by it. After reading through the first book, I wanted to give things a try. We do not have any SystemVerilog licenses here at work, so I decided to...
View ArticleCommunication in UVM register model
I found that UVM register model use semaphore to avoid conflicts, and this may cause some problems: (1) when one sequence is writing some registers, and at the mean time, a UVM_BACK_DOOR is reading...
View Articleuvm-systemc
Hi all, First I apologize if I am using the wrong forum for the question. Please, I would like to know whether someone here could give updates on uvm-sc status. When will a first public release be...
View Articlefunctional coverage for AXI4 WREADY signal
For AXI write transaction axi wready signal determines whether the slave can accept the data. For write burst performance i need to capture the latency between "WREADY" and "next WREADY" signal. For...
View ArticleSystemVerilog Social Club (SVSC) meetup in Santa Clara. May 12th @7pm
SystemVerilog Social Club (SVSC) meetup in Santa Clara. May 12th @7pm. It looks like we may have a guest star at our SVSC meetup next Tuesday. Cliff Cummings. Bring some good questions/problems....
View ArticleUVM_DEBUG verbosity level
Hi, I want to use the "uvm_debug" verbosity but i couldn't find it in uvm1.1/1.2 class reference user guide. Thanks
View ArticleNested do in Questasim
I am using Cygwin to run my commands in a Windows system So from bash prompt I am runnning the command.So Vsim opens in GUI mode and starts executing my script. vsim -i -do "source my_script.tcl" I...
View ArticleFactory override(set_type_override_by_type, set_inst_override_by_type)
Hi All, For set_type_override_by_type and set_inst_override_by_type, I am seeing same definition in uvm user guide as given below. set_type_override_by_type : A convenience function for...
View Articleuvm_config_db/uvm_resource_db
Hi All, Could anyone please let me know why resource is stored in two type of queue in uvm_config_db, The first kind of queues store the handles to the uvm_resource objects that have the common...
View Articleexecution region of UVM TB
Hi All, Simple systemverilog TB execute in re-active region because of program block, But in what region UVM tb executes as we do not use program block in UVM TB ? Thanks, Rahul Kumar
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