Hi,
Here I am attaching a sample code for my doubt:
1) class base_pkt extends uvm_sequence_items;
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endclass
2) class base1_pkt extends base_pkt;
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endclass
3) class base2_pkt extends base1_pkt;
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endclass
4) class my_sqr extends uvm_sequencer#(base_pkt);
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endclass
There are sequences for each packet like seq_base_pkt, seq_base1_pkt, seq_base2_pkt.
The corresponding transaction types provided for the sequences.
Q:- When I run this code by adding required structure. Can I be able to generate all packets to driver through sequencer..?
Regards,
Balakasaiah.