Let's say that I have a VHDL DUT which is a state machine driven by a 50MHz clock (20 ns period).
This state machine has 5 states which advance on every clock, and loops after the final state.
On the final state, it reads an external counter.
Now let's say I want to create a "golden reference" model for the DUT (using SystemC).
Ok so let's see, the only way this would work is if I code a looping thread, that simply waits 100 ns, then reads the counter, and repeats. Agree?
Now fast forward a few months, and the DUT has grown exponentially; it's now a 2000-state state machine, it processes input messages, waits on interrupts, etc.
Yet somewhere buried in it's multi-branch state tree, it still needs to grab the contents of this counter.
Since I have to guarantee they grab the counter value at the same time, am I supposed to inject the actual delay values of the DUT's state machine branches into the reference model?
This sounds like the WRONG thing to do. Thoughts?